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AD1870
REV. A
–
14
–
BCLK
RDEDGE = LO
BCLK
RDEDGE = HI
31
32
1
2
15
16
17
18
19
32
1
2
15
16
17
18
19
32
1
2
MSB-14
LSB
PREVIOUS DATA
MSB-1
LEFT DATA
MSB-2
LSB
RIGHT DATA
SOUT
OUTPUT
ZEROS
ZEROS
MSB-1 MSB-2
LSB
ZEROS
WCLK
OUTPUT
TAG
OUTPUT
MSB
LSB
LEFT TAG
MSB
LSB
RIGHT TAG
MSB
LSB
LEFT TAG
L
R
CK
INPUT
INPUT
MSB
MSB
Figure 7. Serial Data Output Timing: Slave Mode, Right-Justified with No MSB Delay,
S/M = Hl, RLJUST = Hl,
MSBDLY
= Hl
BCLK
RDEDGE = LO
BCLK
RDEDGE = HI
MSB-1
LEFT DATA
MSB
MSB-2
LSB
SOUT
OUTPUT
ZEROS
RIGHT DATA
MSB
MSB-1 MSB-2
LSB
ZEROS
WCLK
INPUT
TAG
OUTPUT
MSB
LEFT TAG
MSB
RIGHT TAG
ZEROS
1
2
3
4
17
1
2
3
4
17
INPUT
L
R
CK
INPUT
LSB
LSB
Figure 8. Serial Data Output Timing: Slave Mode, Data Position Controlled by WCLK Input,
S/
M
= Hl, R
L
JUST = Hl,
MSBDLY
= LO
BCLK
RDEDGE = LO
BCLK
RDEDGE = HI
31
32
1
2
3
4
16
SOUT
OUTPUT
WCLK
OUTPUT
TAG
OUTPUT
LSB
LEFT TAG
LSB
RIGHT TAG
31
32
1
2
3
4
16
MSB-1
LEFT DATA
MSB-2
LSB
MSB
MSB-1
RIGHT DATA
MSB-2
LSB
ZEROS
ZEROS
ZEROS
INPUT
L
R
CK
INPUT
17
18
17
18
MSB
MSB
MSB
Figure 9. Serial Data Output Timing: Slave Mode, Left-Justified with No MSB Delay, S/
M
= Hl,
R
L
JUST = LO,
MSBDLY
= Hl
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